1. Field of Invention
This invention relates to an overlay mark used in IC processes, and more particularly, to an overlay mark for checking the alignment accuracy between a lower layer and a lithography process for defining an upper layer, a method for forming the same, and the application of the same in alignment accuracy checking.
2. Description of the Related Art
As the linewidth of the IC process gets narrower, it is more important to control the critical dimension of the semiconductor device. When an IC process need to form two areas of different pattern arrangements for a layer, two exposure steps constituting a double exposure process are usually performed to the photoresist layer in respective areas to assure that the two areas are defined with predetermined critical dimensions. In order to check the alignment accuracy between the two areas of the layer and an upper layer, an overlay mark is formed prior to the patterning of the upper layer with the following steps in the prior art.
Referring to FIG. 1A, in the exposure step of a first device area 102 of a die 100 using a photomask, two y-directional bar-like exposed regions 112a and 112b are also formed in the photoresist layer 108 on a part 106 of a lower layer in a non-device area. It is noted that for simplicity, the photomask and the lower layer (patterns) and the photoresist layer patterns) in the device areas are all omitted in this figure and all of the following figures.
Referring to FIG. 1B, in the exposure step of the second device area 104, two x-directional bar-like exposed regions 114a and 114b are also formed in the photoresist layer 108 over the part 106 of the lower layer. The photoresist material in the exposed regions 112a, 112b, 114a and 114b and in the exposed regions in the device areas is removed in a subsequent development process, so that two y-directional trenches 122a and 122b and two x-directional trenches 124a and 124b will be formed in the part 106 of the lower layer in the subsequent etching process for forming the patterns of the lower layer in the device areas 102 and 104, as shown in FIG. 1C.
Referring to FIG. 1C, after the upper layer (not shown) is formed, the photoresist patterns in the device areas together with two x-directional and two y-directional photoresist bars 130 as a part of the overlay mark are simultaneously formed. The trenches 122a, 122b, 124a and 124b and the photoresist bars 130 are arranged such that when the lithography process is fully aligned with the first device area 102 in the x-direction, the central line of the two y-directional trenches 122a and 122b and that of the two y-directional photoresist bars 130 defined simultaneously with the first device area 102 coincide with each other, and when the lithography process is fully aligned with the second device area 104 in the y-direction, the central line of the two x-directional trenches 124a and 124b and that of the two x-directional photoresist bars 130 defined simultaneously with the second device area 104 coincide with each other.
Thus, the x-directional alignment accuracy between the lithography process and the first device area 102 can be checked by measuring the distance 132a/132b between the central line of the two y-directional photoresist bars 130 and the y-directional trench 122a/122b, and the y-directional alignment accuracy between the lithography process and the second device area 104 can be checked by measuring the distance 134a/134b between the central line of the two x-directional photoresist bars 130 and the x-directional trench 124a/124b. 
However, using the above overlay mark cannot check the y-directional alignment accuracy between the lithography process and the first device area 102 and the x-directional alignment accuracy between the lithography process and the second device area 104, so that the function of the above overlay mark in alignment accuracy check is not complete.